1. Field of the Invention
Example embodiments of the present invention relate to a method of manufacturing a variable resistance structure and a method of manufacturing a phase-change memory device using the same. More particularly, example embodiments of the present invention relate to a method of manufacturing a variable resistance structure having improved electrical characteristics and a method of manufacturing a phase-change memory device using the same.
2. Description of the Related Art
Generally, semiconductor memory devices are classified into volatile semiconductor memory devices, such as dynamic random-access memory (DRAM) devices or static random-access memory (SRAM) devices, and non-volatile semiconductor memory devices, such as flash memory devices or electrically erasable programmable read-only memory (EEPROM) devices, according to whether data stored in the memory devices is erased or not when power is turned off. Non-volatile semiconductor memory devices, for example, flash memory devices, have been widely employed in portable electronic devices, such as digital cameras, cellular phones, MP3 players, etc. However, since the flash memory device requires a relatively long time to write data or to read stored data, new non-volatile semiconductor memory devices, such as ferroelectric random-access memory (FRAM) devices, magnetic random-access memory (MRAM) devices, and phase-change random-access memory (PRAM) devices, have been developed.
Among the non-volatile semiconductor memory devices, a PRAM device may store data by utilizing a resistance difference between an amorphous phase of a chalcogenide compound and a crystalline phase of the chalcogenide compound. That is, the PRAM device may store the data in states of “0” or “1” using a reversible phase transition of the chalcogenide compound, such as germanium-antimony-tellurium (Ge-Sb-Te; GST), in accordance with the length and width of a pulse applied to the PRAM device. In other words, a reset current required to form the amorphous phase having a relatively high resistance, and a set current required to form the crystalline phase having a relatively low resistance may be transmitted from a transistor to the phase-change material layer through a lower electrode having a relatively small size to generate the phase transition of the chalcogenide compound. An upper portion of the lower electrode is connected to the phase-change material layer and a lower portion of the lower electrode is connected to a contact making electrical contact with the transistor. Here, the contact may be an ohmic contact without a resistance defect. Conventional PRAM devices are disclosed in Korean Patent No. 437,458, Korean Laid-Open Patent Publication No. 2005-31160, U.S. Patent Application Publication No. 2004/02,348,957 and U.S. Pat. No. 6,797,612.
FIGS. 1A to 1E are cross-sectional views illustrating a method of manufacturing a conventional PRAM device.
Referring to FIG. 1A, after a first insulating interlayer 3 of oxide is formed on a semiconductor substrate 1 having contact regions (not shown), the first insulating interlayer 3 is partially etched to form first and second contact holes 6 and 7 that expose the contact regions, respectively.
A first contact 9 and a second contact 10 are formed in the first and the second contact holes 6 and 7. The first and the second contacts 9 and 10 make contact with the contact regions of the semiconductor substrate 1.
Referring to FIG. 1B, after a second insulating interlayer 12 of oxide is formed on the first and the second contacts 9 and 10 and the first insulating interlayer 3, the second insulation interlayer 12 is etched by a photolithography process so that first openings that expose the first and the second contacts 9 and 10 are formed through the second insulation interlayer 12.
A first conductive layer 15 of tungsten is formed on the first and the second contacts 9 and 10 and the second insulating interlayer 12 to fill up the first openings.
Referring to FIG. 1C, the first conductive layer 15 is polished by a chemical mechanical polishing (CMP) process until the second insulating interlayer 12 is exposed, to thereby form a pad 18 and a lower wiring 19. The pad 18 is positioned on the first contact 9 whereas the lower wiring 19 is positioned on the second contact 10.
A nitride layer 21 and an oxide layer 24 are sequentially formed on the second insulating interlayer 12, the pad 18 and the lower wiring 19.
After the oxide layer 24 and the nitride layer 21 are partially etched through a photolithography process to form a second opening 27 exposing the pad 18, a spacer 30 is formed on a sidewall of the second opening 27.
Referring to FIG. 1D, a second conductive layer is formed on the pad 18 and the oxide layer 24 to fill up the opening 27.
The second conductive layer is polished by a CMP process until the oxide layer 24 is exposed, thereby forming a lower electrode 33 filling the second opening 27 on the pad 18. The spacer 30 is positioned between the lower electrode 33 and the sidewall of the second opening 27.
Referring to FIG. 1E, a phase-change material layer pattern 36 and an upper electrode 39 are sequentially formed on the lower electrode 33 and the oxide layer 24.
A third insulating interlayer 42 of oxide is formed on the oxide layer 24 to cover the upper electrode 39.
After an upper contact 45 making contact with the upper electrode 39 is formed through the third insulating interlayer 42, an upper wiring 48 is formed on the upper contact 45 and the third insulating interlayer 42.
In the above-mentioned method of manufacturing the conventional PRAM device, after the first openings are formed through the second insulating interlayer 12 and the first conductive layer 15 is formed on the second insulating interlayer 12 to fill up the first openings, the pad 18 is formed by the CMP process to fill up the first opening. However, a seam or a void may be generated at a central portion of the pad 18 by a growth of tungsten in the processes for forming the first conductive layer 15 and the CMP process.
FIG. 2 is a graph illustrating defects of a metal layer generated in a CMP process. In FIG. 2, “I” indicates corrosion of a metal layer pattern generated in the CMP process, and “II” indicates an over-corrosion of an edge portion of the metal layer pattern in the CMP process.
Referring to FIG. 2, when the metal layer is polished by the CMP process to form the metal layer pattern such as the pad 18, a seam or a void is generated due to the corrosion (I) or the over-corrosion (II) of the metal layer pattern. A size of the seam or the void generated in the metal layer pattern may be greatly increased in a subsequent etching and cleaning processes.
FIGS. 3A to 3C are electron microscopic pictures illustrating a seam generated in a pad of a conventional phase-change memory device. FIG. 4 is an electron microscopic picture illustrating a cross section of the conventional phase-change memory device.
As shown in FIGS. 3A to 3C, although an initial diameter of the seam generated in a pad 18 is about 30 nm, an intermediate diameter of the seam becomes about 42 nm after an etching process. Further, a final diameter of the seam is about 42 nm after a cleaning process. When the seam having an increased size is generated at a central portion of the pad 18, a resistance defect may be generated between the pad 18 and a lower electrode formed on the pad 18. Therefore, electrical characteristics of the PRAM device may be considerably reduced. For example, the number of defects caused by the seam or the void in the pad 18 may make up about 25 to about 80 percent of the total number of defects generated in the PRAM device.